The BoardPerfect Autorouter

The BoardPerfect EDA product range has set a new standard in the electronics industry with high performance, yet easy-to-use layout auto-router tools. BoardPerfect technology analyses physical design complexity and identifies the optimal parameter-cost setting. This moves away from traditional settings-based routing to introduce the concept of analysis-based routing. It allows for more efficient use of routing area and is more suited to handle complex design rules requirements.

Abilities as intell igently assigning vias, adaptive topology-based routing combined with DFM verification is used in an efficient manner to incorporate routing optimization. Higher-density boards can be completed with fewer layers, with the help of BoardPerfect. To do this, BoardPerfect applies multiple-processors to a number of innovative routing algorithms, reducing execution times for PCB routing and verification.

BoardPerfect technology

BoardPerfect technology moves beyond traditional shape-based routing by adding topology-based routing and a board analysis stage to the autorouting process. This allows for more efficient use of routing area and is more suited to handle complex design rules requirements of high density SMD boards and achieve the highest route completion rates.

This eliminates the requirement for the previous expert knowledge, making the routing process transparent and easy. The result gives you the quality of routing frequently associated with manually routed designs, plus completion rates normally only associated with auto-routers much more expensive.

Adaptive technology

The adaptive rip-up and retry technology provides BoardPerfect with an iterative process of self-correction. At each pass, the router 'learns' and attempts to route the connections until the router has completed its task. Results using t his technology are better because the router has a chance to self correct and rework its own routing path, thus improving the quality of the routes.

Concurrent DFM verification

DFM vault grade

A measurement of the efficiency of test vectors to detect manufacturing defects. The real-time Design for Manufacturability (DFM) fault-grade value is presented as a percentage of the faults that can be identified using the build in test vectors.

Bus routing technology

A design auto-routing methodology where portions of large designs are divided into manageable sections. The collection of connections between two components is routed with multiple sorting algorithms to form clean and structured bus structures.

DFM test vectors

  • Vias under components
  • Number of vias
  • Overall Track- length / bus-length
  • Design-rule incompliance
  • Acid Traps
  • Via in pin channels
  • Pin to pin channels
  • Route that creates Net Antenna
  • Route that create a loop
  • Route that creates Reflow Heat-sink
  • Via close to board-edge
  • Blind or buried via
  • Via in power route
  • Via closely connected to pad

DFM rules are meant to prevent problems from arising during layout and physical verification, before the design gets to manufacturing. DFM rules gives the router guidelines and the ability to automatically mimic a designer's manual edits to form clean and structured wires.

DRC (Design Rule Check)

The program verify that the layout of wires which have undergone autorouting and cleanup does not violate any rules associated with the CAD design technology. It includes electrical rule checkers (ERC), which verify that no electrical rule violations have occurred.

Topological technology

With shape-based technology all board elements are modelled as basic geometric rectangular shapes. Each shape can have design rules such as width and clearance to enforce design constraints.

Using topology-based routing also means the real shape of obstacles within the design can be identified and avoided during routing.

The benefits of topology-based technology are clear as it accurately models shape with exact dimensions. This utilizes all of the available space and accommodates mixed and fine pin pitches, pad or trace size.

BoardPerfect is capable of routing the finest pitched devices and highest routing density.

Advanced design rules

With the advanced conditional rules, it is possible to establish very stringent requirements within an area or between objects such as classes or layers, in the design. Smaller and more complex packaging technologies place new demands on auto-routing.

Scoping desing rules

Critical nets may easily be tagged into a class. It may be desirable, for example, to provide extra clearance between a class of analog nets and a class of clock nets. Similarly, if it is necessary to maintain specific net impedance, trace width rules can be set for an individual layer. So for example, a net may be assigned a default width, but could be reduced to when entering a region.

The Advanced Rules extends the basic rule assignment routines to allow several refinements for control of more complex designs during auto-routing. The design rules collectively form an instruction set for BoardPerfect to follow.

Designs can also require specific requirements to individual nets or regions of the board as well as considering such issues as crosstalk, reflections and net lengths.

Rules by Region. Another approach to routing in congested device pad areas is to define different, smaller rules within a limited region.

Advanced rules set provides:

  • Expanded rules hierarchy
  • Layer, net-class, padstack, groups, regions
  • Gap, min/max length, matched length
  • Added conditional rules between objects
  • Class to class, class to net, From To Net
  • Component pad entry rules
  • Clearances, fanout patterns, and more
  • Neck-Down trace width/ clearance rules

Rules hierarchy

All rules are resolved by the priority setting. During auto-routing, the BoardPerfect goes through the rules from highest to lowest priority and picks the first one whose scope expressions match the objects being routed.


  • None
  • Pcb
  • layer
  • Class
  • Class_Layer
  • Group_Set
  • Group_Set_Layer
  • Net
  • Net_Layer
  • Group
  • Group_Layer
  • FromTo
  • FromTo_Layer
  • Class_Class
  • Class_Class_Layer
  • Padstack
  • Region
  • Class_Region
  • Net_Region
  • Class_Class_Region
  • NeckDown_Region

Clearance types

  • expose_all
  • pin_pin
  • pin_smd
  • smd_smd
  • pin_wire
  • smd_wire
  • wire_wire
  • smd_via
  • pin_via
  • via_wire
  • via_via

The smd_via clearance is defined as the minimum clearance from the SMD pad to the first via.

The via_via clearance is defined as the minimum clearance between any two vias on the same net and the same layer.

For instance, starting with default values for the entire board, critical nets may easily be tagged into a class and assigned rules that override the defaults. Within that class, a net may be assigned a value overriding the class default.

Automatic trace neckdown

Analyzed outside the context of the auto-router, BoardPerfect recognizes the design footprints and chooses the Neck-down trace width and clearance most appropriate for the SMD component. BoardPerfect calculates the maximum ratio of the trace to the SMD pad, based on the SMD pin-pitch and pad size.

This is expressed as a region design rule. The SMD pads are automatically enclosed within a design rule region to perform the neck-down. If the neck-down is set to 'Auto' that the neck-down is performed if desired (e.g. 20 mil power trace to a 10 mil SMD pad). With the 'Enabled' mode the neck-down is always created for all SMD pads.

This enables the designer to handle fabrication yield requirements like heat-distribution.

Fanout escape routing

The effectiveness of a fanout pattern contributes significantly to the route-ability of a design, which impacts the layer count and affects the cost of the board fabrication, while maintaining signal integrity and fabrication yield requirements. The fanout is a part of the routing solution, which may also include escape traces and general interconnect routing of the pins.

Analyzed outside the context of the auto-router, BoardPerfect recognizes the design SMD footprints and chooses the style most appropriate for the component technology..

During fanout, the autorouter gathers information and learns about the problem areas where conflicts exist to eliminate.

Even though it sometimes uses a large number of routing passes, the autorouter usually achieves a high fanout completion rate.

SMD footprint recognition

Because the physical footprints are not described in the Specctra design format, BoardPerfect performs footprint recognition to extract the footprint though pattern recognition algorithms. This gives the autorouter the ability to choose the best fanout and neck-down style most appropriate for the component technology. Please note that the build in pattern recognition algorithms aim to provide a reasonable answer for all possible inputs and to perform "most likely" matching of the inputs, taking into account the variation in footprints. Therefore; it is important to verify the results as listed in the properties design rules and update the package type if applicable.